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RTL FPGA Engineer with HAPS prototyping experience Experience: 5-10Yrs Work location: Bangalore

Roles and Responsibilities: 5–10 years’ hands-on experience with Synopsys HAPS boards and ProtoCompiler/Identify Debug. Strong RTL design/verification skills in Verilog/SystemVerilog. Proven FPGA implementation expertise: synthesis, floorplanning, SDC constraints, and timing closure. Board-level bring-up/debug using JTAG, oscilloscopes, logic analyzers; solid clocks/resets/power understanding. Interface bring-up experience with PCIe, DDR, Ethernet, and common serial buses (UART/SPI/I2C). Scripting proficiency in TCL, Python, and Shell for flow automation. Excellent problem-solving, cross-functional communication, and documentation skills.

Job Description

Role :

RTL FPGA Engineer with HAPS prototyping experience Roles and Responsibilities :

Experience: 5-10Yrs

Work location: Bangalore

5–10 years’ hands-on experience with Synopsys HAPS boards and ProtoCompiler/Identify Debug. Strong RTL design/verification skills in Verilog/SystemVerilog.

Proven FPGA implementation expertise: synthesis, floorplanning, SDC constraints, and timing closure.

Board-level bring-up/debug using JTAG, oscilloscopes, logic analyzers; solid clocks/resets/power understanding.

Interface bring-up experience with PCIe, DDR, Ethernet, and common serial buses (UART/SPI/I2C). Scripting proficiency in TCL, Python, and Shell for flow automation.

Excellent problem-solving, cross-functional communication, and documentation skills.

Senior Emulation/Prototyping Engineers

Experience : 4-5 years

Location : Bangalore

experience in emulation/prototyping using Cadence/Synopsys tool flows (Palladium/Protium/HAPS/Zebu)

2. Working knowledge of System Verilog & Verilog language semantics and compilation flows

3. Solid understanding on SOC architecture and AXI protocol

4. Good communication skills and team collaboration

Interested,please drop your updated resume to janagaradha.n@acldigital.com